[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add option to compress postcar stage

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36674 )

Change subject: arch/x86: Add option to compress postcar stage
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Patch Set 1:
> It's not cached ATM. Something like CB:34992 could do it however. So the question is whether decompressing to uncached ram is worth the size reduction and therefore slow SPI reads. I guess this needs measuring.

Yeah, you can profile it, but in my experience, decompressing in uncached memory is prohibitively slow. I mean, fundamentally, all it does is memcpy() small amounts from the previously written areas over and over again.