[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/mendocino: update FSP parameters for eDP power sequence adjus...

[Chris Wang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Chris Wang, Fred Reitberger, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74757

to look at the new patch set (#3).

Change subject: soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment
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soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment

Update UPD structure to align with MDN-FSP. Also, rename the UDP name to
match the eDP sequence timing in ms.

1. Set edp_panel_t8_ms for varybl to blon.
2. Set edp_panel_t9_ms for bloff to varybloff.

BUG=b:271704149
BRANCH=none
Test=Build/Boot to ChromeOS

Signed-off-by: Chris Wang 
Change-Id: Id410c40a65c0fd4b9b73cf36dc1f08eba0a3e44c
---
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fsp_m_params.c
M src/vendorcode/amd/fsp/mendocino/FspmUpd.h
3 files changed, 29 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74757/3