Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62101 )
Change subject: nb/amd/amdfam10/bootblock.c: Cosmetic changes ......................................................................
nb/amd/amdfam10/bootblock.c: Cosmetic changes
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ia618827f975c97a492977c12383c95f608f00e08 --- M src/northbridge/amd/amdfam10/bootblock.c 1 file changed, 16 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/62101/1
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 547eff6..e87180a 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -43,13 +43,12 @@ /* CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. */ }
-static void ht_chain_finalize(int ht_dev_num, u8 unitid, u8 pos, u8 end_used) +static void ht_chain_finalize(int ht_dev_num, u8 unitid, u8 pos, bool end_used) { if (CONFIG_HT_CHAIN_END_UNITID_BASE == 0x20) return;
- if ((ht_dev_num > 1) && (unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && - (end_used == 0)) { + if ((ht_dev_num > 1) && (unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { u16 flags; flags = pci_read_config16(PCI_DEV(0, unitid, 0), pos + PCI_CAP_FLAGS); flags &= ~HT_PRIMARY_BASE_UNIT_ID_MASK; @@ -99,21 +98,21 @@ if (CONFIG_HT_CHAIN_UNITID_BASE == 0) return;
- /* + /* * Assumption the HT chain that is bus 0 has the HT I/O Hub on it. On * most boards this just happens. If a CPU has multiple non Coherent * links the appropriate bus registers for the links needs to be * programed to point at bus 0. */ u8 next_unitid, last_unitid = 0; - /* + /* * Let's record the device of last ht device, So we can set the Unitid * to CONFIG_HT_CHAIN_END_UNITID_BASE */ u8 real_last_unitid = 0; u8 real_last_pos = 0; int ht_dev_num = 0; /* except host_bridge */ - u8 end_used = 0; + bool end_used = false;
next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { @@ -121,7 +120,7 @@ u8 pos; last_unitid = next_unitid;
- id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID); + id = pci_read_config32(PCI_DEV(0, 0, 0), PCI_VENDOR_ID); /* If the chain is enumerated quit */ if (id == 0 || id == ULONG_MAX) { ht_chain_finalize(ht_dev_num, real_last_unitid, real_last_pos, @@ -129,7 +128,7 @@ return; }
- pos = pci_s_find_capability(PCI_DEV(0,0,0), PCI_CAP_ID_HT); + pos = pci_s_find_capability(PCI_DEV(0, 0, 0), PCI_CAP_ID_HT);
while (pos != 0) { u16 flags; @@ -137,9 +136,9 @@ * Read and write and reread flags so the link * direction bit is valid. */ - flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); - pci_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); - flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); + flags = pci_read_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS); + pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); + flags = pci_read_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS); if (pci_cap_is_ht_primary(pos)) { u8 count; u8 ctrl, ctrl_off; @@ -148,12 +147,10 @@ if (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20) { if (next_unitid >= 0x18 && !end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; - end_used = 1; + end_used = true; } else if (next_unitid >= 0x18 && end_used) { - ht_chain_finalize(ht_dev_num, - real_last_unitid, - real_last_pos, - end_used); + ht_chain_finalize(ht_dev_num, real_last_unitid, + real_last_pos, end_used); return; } real_last_unitid = next_unitid; @@ -174,7 +171,8 @@ devx = PCI_DEV(0, next_unitid, 0); next_unitid += count;
- pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); + pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, + flags);
/* Test for end of chain */ ctrl_off = (flags & HT_CMD_MASTER_OR_SLAVE) ? @@ -195,7 +193,7 @@
break; } - pos = pci_s_find_next_capability(PCI_DEV(0,0,0), PCI_CAP_ID_HT, 0); + pos = pci_s_find_next_capability(PCI_DEV(0, 0, 0), PCI_CAP_ID_HT, 0); } } while (last_unitid != next_unitid); }