[coreboot-gerrit] Change in coreboot[master]: memory_info: Rename ddr_frequency to ddr_speed_mts

[Rob Barnes (Code Review)]

Hello build bot (Jenkins), Raul Rangel, David Guckian, Vanessa Eusebio, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44549

to look at the new patch set (#3).

Change subject: memory_info: Rename ddr_frequency to ddr_speed_mts
......................................................................

memory_info: Rename ddr_frequency to ddr_speed_mts

This is correcting a legacy misnaming of this field. From SMBIOS 3.0
spec:
   Memory speed is expressed in megatransfers per second (MT/s). Previous revisions (3.0.0 and earlier) of
   this specification used MHz to indicate clock speed. With double data rate memory, clock speed is distinct
   from transfer rate, since data is transferred on both the rising and the falling edges of the clock signal.
   This maintains backward compatibility with observed DDR implementations prior to this revision, which
   already reported transfer rate instead of clock speed, e.g., DDR4-2133 (PC4-17000) memory was
   reported as 2133 instead of 1066.

This change is symantec only, no logical change.

Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25
Signed-off-by: Rob Barnes 
---
M src/arch/x86/smbios.c
M src/device/dram/ddr3.c
M src/device/dram/ddr4.c
M src/drivers/intel/fsp1_1/romstage.c
M src/include/memory_info.h
M src/mainboard/google/cyan/spd/spd.c
M src/soc/amd/common/block/pi/amd_late_init.c
M src/soc/amd/picasso/dmi.c
M src/soc/intel/broadwell/include/soc/pei_data.h
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/common/smbios.c
M src/soc/intel/denverton_ns/hob_mem.c
12 files changed, 26 insertions(+), 23 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44549/3