[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Enable CSME/PMC/P2SB/SMBus

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30465

Change subject: mb/google/hatch: Enable CSME/PMC/P2SB/SMBus
......................................................................

mb/google/hatch: Enable CSME/PMC/P2SB/SMBus

* Enable host bridge.
* Enable CSME.
* Enable Power Management Controller.
* Enable Primary to Side Band Bridge Controller.
* Enable SmBus Controller.

BUG=b:120914069
BRANCH=None
TEST= code compiles with the changes

Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee
Signed-off-by: Rizwan Qureshi 
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30465/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index a996a70..e59ccc1 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -41,7 +41,7 @@
    register "SkipExtGfxScan" = "1"

device domain 0 on
-		device pci 00.0 off end # Host Bridge
+		device pci 00.0 on end # Host Bridge
    	device pci 02.0 on  end # Integrated Graphics Device
    	device pci 04.0 off end # SA Thermal device
    	device pci 12.0 off end # Thermal Subsystem
@@ -61,7 +61,7 @@
    	device pci 15.1 off end # I2C #1
    	device pci 15.2 off end # I2C #2
    	device pci 15.3 off end # I2C #3
-		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
    	device pci 16.1 off end # Management Engine Interface 2
    	device pci 16.2 off end # Management Engine IDE-R
    	device pci 16.3 off end # Management Engine KT Redirection
@@ -97,10 +97,10 @@
    	end # GSPI #0
    	device pci 1e.3 off end # GSPI #1
    	device pci 1f.0 on end # LPC/eSPI
-		device pci 1f.1 off end # P2SB
-		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
    	device pci 1f.3 off end # Intel HDA
-		device pci 1f.4 off end # SMBus
+		device pci 1f.4 on  end # SMBus
    	device pci 1f.5 on  end # PCH SPI
    	device pci 1f.6 off end # GbE
    end