build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30907 )
Change subject: soc/intel/cannonlake: Add processor power limits control support ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h@206 PS1, Line 206: uint32_t tdp_psyspl2; code indent should use tabs where possible
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h@206 PS1, Line 206: uint32_t tdp_psyspl2; please, no spaces at the start of a line
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h@208 PS1, Line 208: uint32_t tdp_psyspl3; code indent should use tabs where possible
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h@208 PS1, Line 208: uint32_t tdp_psyspl3; please, no spaces at the start of a line
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h@209 PS1, Line 209: /* SysPL3 window size */ code indent should use tabs where possible
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h@210 PS1, Line 210: uint32_t tdp_psyspl3_time; code indent should use tabs where possible
https://review.coreboot.org/#/c/30907/1/src/soc/intel/cannonlake/chip.h@210 PS1, Line 210: uint32_t tdp_psyspl3_time; please, no spaces at the start of a line