Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45050 )
Change subject: soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment. ......................................................................
Patch Set 7:
(4 comments)
Patch Set 7:
comments need to be resolved
https://review.coreboot.org/c/coreboot/+/45050/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45050/3//COMMIT_MSG@16 PS3, Line 16: 3247427
Think you need a chrome-internal: here as well.
Ack
https://review.coreboot.org/c/coreboot/+/45050/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45050/5//COMMIT_MSG@9 PS5, Line 9: Previous commit
Please reference the commit by hash and commit message summary.
Ack
https://review.coreboot.org/c/coreboot/+/45050/5//COMMIT_MSG@9 PS5, Line 9: Previous commit misinterpreted spec as requiring size alignment on all : IVHD device entries.
Please summarize the issue this causes (hang where?).
Ack
https://review.coreboot.org/c/coreboot/+/45050/3/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/45050/3/src/soc/amd/picasso/acpi.c@... PS3, Line 64: 32
Is it always 32? Should we have some defines for how many IRQs are supported in each apic?
Will use the defs for ioapic irq number in the MADT part i split off. That one requires a bit more work inside FSP.