Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38514 )
Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet ......................................................................
soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
This patch updates SA DRAM registers bit definitions as per SKL datasheet vol 2, doc 332688.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38514 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/acpi/systemagent.asl 1 file changed, 5 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 920062c..e430b43 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -32,26 +32,27 @@ Offset(0x40), /* EPBAR (0:0:0:40) */ EPEN, 1, /* Enable */ , 11, - EPBR, 20, /* EPBAR [31:12] */ + EPBR, 27, /* EPBAR [38:12] */
Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ , 14, - MHBR, 17, /* MCHBAR [31:15] */ + MHBR, 24, /* MCHBAR [38:15] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ PXSZ, 2, /* PCI Express Size */ , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ + PXBR, 13, /* PCI Express BAR [38:26] */
Offset(0x68), /* DMIBAR (0:0:0:68) */ DIEN, 1, /* Enable */ , 11, - DIBR, 20, /* DMIBAR [31:12] */ + DIBR, 27, /* DMIBAR [38:12] */
Offset (0x70), /* ME Base Address */ MEBA, 64, + Offset (0xa0), TOM, 64, /* Top of Used Memory */ TUUD, 64, /* Top of Upper Used Memory */