[coreboot-gerrit] Change in ...coreboot[master]: cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at...

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33015

Change subject: cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at 0x35
......................................................................

cpu/intel/{haswell,model_206ax}: Use MSR_CORE_THREAD_COUNT for msr at 0x35

Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register
name of the msr at 0x35 is MSR_CORE_THREAD_COUNT.

Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
4 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/33015/1

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 3dfdd8d..4ebbe18 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -34,7 +34,7 @@
 /* Haswell bus clock is fixed at 100MHz */
 #define HASWELL_BCLK			100

-#define CORE_THREAD_COUNT_MSR		0x35
+#define MSR_CORE_THREAD_COUNT		0x35
 #define MSR_FEATURE_CONFIG		0x13c
 #define MSR_FLEX_RATIO			0x194
 #define  FLEX_RATIO_LOCK		(1 << 20)
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 25cf243..95d719c 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -732,7 +732,7 @@
    int num_threads;
    int num_cores;

-	msr = rdmsr(CORE_THREAD_COUNT_MSR);
+	msr = rdmsr(MSR_CORE_THREAD_COUNT);
    num_threads = (msr.lo >> 0) & 0xffff;
    num_cores = (msr.lo >> 16) & 0xffff;
    printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index f4c5d93..c0d2434 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -22,7 +22,7 @@
 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
 #define SANDYBRIDGE_BCLK		100

-#define CORE_THREAD_COUNT_MSR		0x35
+#define MSR_CORE_THREAD_COUNT		0x35
 #define MSR_FEATURE_CONFIG		0x13c
 #define MSR_FLEX_RATIO			0x194
 #define  FLEX_RATIO_LOCK		(1 << 20)
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 524e49c..80d85f3 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -513,7 +513,7 @@
    int num_threads;
    int num_cores;

-	msr = rdmsr(CORE_THREAD_COUNT_MSR);
+	msr = rdmsr(MSR_CORE_THREAD_COUNT);
    num_threads = (msr.lo >> 0) & 0xffff;
    num_cores = (msr.lo >> 16) & 0xffff;
    printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",