[coreboot-gerrit] [S] Change in coreboot[master]: [TESTONLY] soc/intel/apollolake: Write to PCI config XHCLKGTEN

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67316 )

Change subject: [TESTONLY] soc/intel/apollolake: Write to PCI config XHCLKGTEN
......................................................................

[TESTONLY] soc/intel/apollolake: Write to PCI config XHCLKGTEN

Documentation says that the XHCLKGTEN register in the XHCI MMIO space is
a "dummy register, mirror of physical register as XHCLKGTEN". So, try to
write to the XHCLKGTEN register in the XHCI PCI config space.

Change-Id: I05f5490fdb949f68bac16602ab94e0226854b38c
Signed-off-by: Angel Pons 
---
M src/soc/intel/apollolake/chip.c
1 file changed, 16 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/67316/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index bbf0564..6bb4c64 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -866,19 +866,12 @@
    	 * mitigate USB device suspend and resume failure.
    	 */
    	if (CONFIG(SOC_INTEL_GEMINILAKE)) {
-			uint32_t *cfg;
-			const struct resource *res;
-			uint32_t reg;
-			struct device *xhci_dev = PCH_DEV_XHCI;
-
-			res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
-			cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN);
-			reg = SRAMPGTEN | SSLSE | USB2PLLSE | IOSFSTCGE |
+			uint32_t reg = SRAMPGTEN | SSLSE | USB2PLLSE | IOSFSTCGE |
    			HSTCGE | HSUXDMIPLLSE | SSTCGE | XHCFTCLKSE |
    			XHCBBTCGIPISO | XHCUSB2PLLSDLE | SSPLLSUE |
    			XHCBLCGE | HSLTCGE | SSLTCGE | IOSFBTCGE |
    			IOSFGBLCGE;
-			write32(cfg, reg);
+			pci_write_config32(PCH_DEV_XHCI, 0x50, reg);
    	}

/* Disable XHCI LFPS power management if the option in dev tree is set. */