[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update interrupt setting

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40872

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

soc/intel/tigerlake: Update interrupt setting

Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer.  Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.

Signed-off-by: Wonkyu Kim 
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/include/soc/irq.h
2 files changed, 10 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40872/3