[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )

Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
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Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39538/12//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39538/12//COMMIT_MSG@11 
PS12, Line 11: PcieRpL1Substates to devicetree to allow boards to set these options.
> Do you know what the default is?

From Fsp.bsf:
PcieRpAspm defaults to 0x4 - autoconfig.
PcieRpL1Substates defaults to 0x3 - 'MAX,' a pseudo-value that ends the enum (PCH_PCIE_L1SUBSTATES_CONTROL, see https://github.com/andreiw/lampone-edk2-platforms/blob/master/Silicon/Intel/...), mapping to SS_L1_2.

The indirection is needed because 0x0 is "disabled."