Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40872 )
Change subject: soc/intel/tigerlake: Update interrupt setting ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/irq.h:
https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... PS1, Line 14: #define LPSS_I2C1_IRQ 40
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Done
https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... PS1, Line 22: #define LPSS_SPI3_IRQ 43
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Done
https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... PS1, Line 23: #define LPSS_UART0_IRQ 16
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Done
https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... PS1, Line 24: #define LPSS_UART1_IRQ 17
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Done