Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/36463/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36463/1//COMMIT_MSG@12 PS1, Line 12: : TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify : S0/S3/S4/S5 entries after booting to OS. It should even result in identical binaries. You can compare the hashes when build with BUILD_TIMELESS=1. That might speed up testing.
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... PS1, Line 17: : Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) : Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) : Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) : Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) Those have been the same for a very long time on Intel targets? Maybe move it to southbridge/intel/common/acpi (I don't care that much though where it ends ) and replace
southbridge/intel/i82801gx/acpi/sleepstates.asl southbridge/intel/bd82x6x/acpi/sleepstates.asl southbridge/intel/i82801ix/acpi/sleepstates.asl southbridge/intel/lynxpoint/acpi/sleepstates.asl southbridge/intel/fsp_rangeley/acpi/sleepstates.asl southbridge/intel/i82801jx/acpi/sleepstates.asl soc/intel/baytrail/acpi/sleepstates.asl soc/intel/fsp_baytrail/acpi/sleepstates.asl soc/intel/apollolake/acpi/sleepstates.asl soc/intel/braswell/acpi/sleepstates.asl soc/intel/broadwell/acpi/sleepstates.asl soc/intel/cannonlake/acpi/sleepstates.asl soc/intel/denverton_ns/acpi/sleepstates.asl soc/intel/skylake/acpi/sleepstates.asl soc/intel/icelake/acpi/sleepstates.asl\
Make sure to make the _S3 entry depend on HAVE_ACPI_RESUME with CPP.