[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41155 )

Change subject: soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G
......................................................................

soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G

This change sets the base for MMIO above 4G to TOUDD. It matches what
is used by resource allocator if MMIO resources are allocated above 4G
and also matches the expectation in northbridge.asl.

BUG=b:149186922
TEST=Verified that kernel does not complain about MMIO windows above
4G.

Signed-off-by: Furquan Shaikh 
Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383
---
M src/soc/intel/common/block/systemagent/systemagent.c
1 file changed, 31 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41155/1

diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index d0e171d..9354c25 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -42,34 +42,6 @@
 }

/*
- * This function will get above 4GB mmio enable config specific to soc.
- *
- * Return values:
- *  0 = Above 4GB memory is not enable
- *  1 = Above 4GB memory is enable
- */
-static int get_enable_above_4GB_mmio(void)
-{
-	const struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
-	return common_config->enable_above_4GB_mmio;
-}
-
-/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(global_nvs_t *gnvs)
-{
-	if (get_enable_above_4GB_mmio()) {
-		gnvs->e4gm = 1;
-		gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS;
-		gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
-		printk(BIOS_DEBUG,
-			"PCI space above 4GB MMIO is from 0x%llx  to len = 0x%llx\n",
-				gnvs->a4gb, gnvs->a4gs);
-	}
-}
-
-/*
  * Add all known fixed MMIO ranges that hang off the host bridge/memory
  * controller device.
  */
@@ -125,6 +97,37 @@
    *result = value;
 }

+/*
+ * This function will get above 4GB mmio enable config specific to soc.
+ *
+ * Return values:
+ *  0 = Above 4GB memory is not enable
+ *  1 = Above 4GB memory is enable
+ */
+static int get_enable_above_4GB_mmio(void)
+{
+	const struct soc_intel_common_config *common_config;
+	common_config = chip_get_common_soc_structure();
+
+	return common_config->enable_above_4GB_mmio;
+}
+
+/* Fill MMIO resource above 4GB into GNVS */
+void sa_fill_gnvs(global_nvs_t *gnvs)
+{
+	if (!get_enable_above_4GB_mmio())
+		return;
+
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+
+	gnvs->e4gm = 1;
+	sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb);
+	gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
+	printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx  to len = 0x%llx\n",
+	       gnvs->a4gb, gnvs->a4gs);
+}
+
+
 static void sa_get_mem_map(struct device *dev, uint64_t *values)
 {
    int i;