Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46394 )
Change subject: mb/google/asurada: fix EC commands timeout ......................................................................
mb/google/asurada: fix EC commands timeout
The Asurada EC is using the large packet (256B) mode, and we were seeing lots of timeout errors on various commands.
The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000, and that is too small for large packet running in 1M so we should change EC SPI to the same value that kernel is using (3M).
BUG=b:161509047 TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot
Signed-off-by: Hung-Te Lin hungte@chromium.org Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46394 Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/asurada/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 04e8898..647555a 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -7,7 +7,7 @@
void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); setup_chromeos_gpios(); gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING);