David Hendricks (dhendrix@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5798
-gerrit
commit f9efa0afb75fb0f1e2884b434c6dc4f04540369e Author: David Hendricks dhendrix@chromium.org Date: Tue May 20 15:52:08 2014 -0700
baytrail: Fix some minor errors in FSP
- Duplicate declaration of GetFspReservedMemoryFromGuid - Corrupt line that was only compiled for a southbridge that no board in coreboot currently uses.
(thanks for Mike Hibbett mhibbett@ircona.com for pointing this out)
Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6 Signed-off-by: David Hendricks dhendrix@chromium.org --- src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 2 +- src/vendorcode/intel/fsp/baytrail/include/fspplatform.h | 9 +-------- 2 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index f7bb023..0537c54 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -89,7 +89,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams,
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data);/home/martin/extra/git/coreboot + GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data); ConfigureDefaultUpdData(fsp_upd_data); #else pFspRtBuffer->Platform.MemoryConfig = &MemoryConfig; diff --git a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h index 1b5fca1..81f7b66 100644 --- a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h +++ b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h @@ -75,11 +75,4 @@ GetLowMemorySize ( uint32_t *LowMemoryLength );
-void -GetFspReservedMemoryFromGuid ( - uint32_t *FspMemoryBase, - uint32_t *FspMemoryLength, - EFI_GUID FspReservedMemoryGuid - ); - -#endif \ No newline at end of file +#endif