[coreboot-gerrit] Change in coreboot[master]: soc/amd: factor out PM_DECODE_EN register definitions

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48433 )

Change subject: soc/amd: factor out PM_DECODE_EN register definitions
......................................................................

soc/amd: factor out PM_DECODE_EN register definitions

Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
3 files changed, 11 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 62f7190..3887f73 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -11,6 +11,17 @@
 #define PM_DATA				0xcd7

/*
+ * Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7. Valid for Mullins and
+ * newer SoCs, but not for the generations with separate FCH or Kabini.
+ */
+#define PM_DECODE_EN			0x00
+#define   SMBUS_ASF_IO_EN		(1 << 4)
+#define   CF9_IO_EN			(1 << 1)
+#define   LEGACY_IO_EN			(1 << 0)
+
+#define SMB_ASF_IO_BASE			0x01 /* part of PM_DECODE_EN */
+
+/*
  * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs
  * and the Kabini SoC fall into this category. Kabini's successor, Mullins, uses
  * this newer method of enable in PMx04.
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index c0a5057..13ef53f 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -22,11 +22,6 @@
 #define   SMB_UART_1_8M_SHIFT		28

/* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
-#define PM_DECODE_EN			0x00
-#define   SMBUS_ASF_IO_EN		BIT(4)
-#define   CF9_IO_EN			BIT(1)
-#define   LEGACY_IO_EN			BIT(0)
-#define SMB_ASF_IO_BASE			0x01 /* part of PM_DECODE_EN in PPR */
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 78fe583..a4f43ec 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -15,15 +15,10 @@
  */

/* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
-#define PM_DECODE_EN			0x00
-#define   CF9_IO_EN			BIT(1)
-#define   LEGACY_IO_EN			BIT(0)
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 #define   FORCE_STPCLK_RETRY		BIT(24)

-#define SMB_ASF_IO_BASE			0x01 /* part of PM_DECODE_EN */
-
 #define PWR_RESET_CFG			0x10
 #define   TOGGLE_ALL_PWR_GOOD		BIT(1)