[coreboot-gerrit] Change in coreboot[master]: riscv: add support to check ISA extension

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27410

Change subject: riscv: add support to check ISA extension
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riscv: add support to check ISA extension

Add support to check ISA extension for RISC-V.

Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/include/arch/encoding.h
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27410/1

diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index f84c9d4..94cb422 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -239,6 +239,11 @@
 #define rdcycle() read_csr(cycle)
 #define rdinstret() read_csr(instret)

+static inline int supports_extension(char ext)
+{
+	return read_csr(misa) & (1 << (ext - 'A'));
+}
+
 #endif

#endif