Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48632 )
Change subject: soc/amd/picasso: Fix ACPI PCI routing table
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Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48632/4/src/soc/amd/picasso/pcie_gp...
File src/soc/amd/picasso/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/48632/4/src/soc/amd/picasso/pcie_gp...
PS4, Line 103: % 8
I don't understand where this `% 8` here comes from, especially considering the `* 4` in `calculate_ […]
Take GPP6 INTC for example, 6 * 4 + 2 = 26. That would be the redirection table entry in the NB-IOAPIC. This is then reduced mod 8 and passed into the the FCH-IOAPIC because the FCH-IOAPIC only has 8 INTx lines. i.e. INT[A-H].
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