[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Move GPIO PM configuration to soc level

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37685 )

Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level
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Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37685/11/src/soc/intel/common/acpi/... 
File src/soc/intel/common/acpi/platform.asl:

https://review.coreboot.org/c/coreboot/+/37685/11/src/soc/intel/common/acpi/... 
PS11, Line 22: External(_SB.PCI0.EGPM, MethodObj)
> > > but I feel like each mainboard should be able to choose if it wants to change the PM bits at S0i […]

But, the implementation is conflating the "override of GPIO PM bits in coreboot" and "save/restore PM bits across S0ix entry/exit". As I understand it, the config in devicetree currently is meant to indicate to common SoC code that the mainboard wants to use its own version of GPIO PM bits when booting up.