[coreboot-gerrit] Patch set updated for coreboot: 2b6d7da baytrail: Enable PCIe common clock and ASPM

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5051

-gerrit

commit 2b6d7daec5b83c49a254aadcb8d7e9e3ddca1562
Author: Duncan Laurie 
Date:   Thu Jan 16 11:18:36 2014 -0800

baytrail: Enable PCIe common clock and ASPM

Enable the config options to have the device enumeration layer configure
    common clock and ASPM for endpoints.

BUG=chrome-os-partner:23629
    BRANCH=baytrail
    TEST=build and boot on rambi, check PCIe for ASPM and common clock:

lspci -vv -s 0:1c.0 | grep LnkCtl:
     LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

lspci -vv -s 1:00.0 | grep LnkCtl:
     LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f
    Signed-off-by: Duncan Laurie 
    Reviewed-on: https://chromium-review.googlesource.com/182860
    Reviewed-by: Aaron Durbin 
    Signed-off-by: Aaron Durbin 
---
 src/soc/intel/baytrail/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 9a3fa92..a93b487 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -24,6 +24,8 @@ config CPU_SPECIFIC_OPTIONS
    select MMCONF_SUPPORT_DEFAULT
    select RELOCATABLE_MODULES
    select PARALLEL_MP
+	select PCIEXP_ASPM
+	select PCIEXP_COMMON_CLOCK
    select SMM_MODULES
    select SMM_TSEG
    select SMP