[coreboot-gerrit] Change in coreboot[master]: mb/google/drallion: modify PCIE setting

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35243 )

Change subject: mb/google/drallion: modify PCIE setting
......................................................................

mb/google/drallion: modify PCIE setting

Based on HW schematic to modify PCIE setting.

BUG=b:138082886
BRANCH=N/A
TEST=N/A

Signed-off-by: Eric Lai 
Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243
Tested-by: build bot (Jenkins) 
Reviewed-by: Mathew King 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 18 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mathew King: Looks good to me, approved

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 8870126..561217a 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -189,22 +189,27 @@
    	},
    }"

+	# PCIe port 9 for Card Reader
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[4]" = "8"
+	register "PcieClkSrcClkReq[4]" = "4"
+
    # PCIe port 10 for M.2 2230 WLAN
    register "PcieRpEnable[9]" = "1"
-	register "PcieClkSrcUsage[2]" = "9"
-	register "PcieClkSrcClkReq[2]" = "2"
-
-	# PCIe port 11 for card reader
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpLtrEnable[10]" = "1"
-	register "PcieClkSrcUsage[1]" = "10"
+	register "PcieClkSrcUsage[1]" = "9"
    register "PcieClkSrcClkReq[1]" = "1"

+	# PCIe port 12 for M.2 3042 WWAN
+	register "PcieRpEnable[11]" = "1"
+	register "PcieClkSrcUsage[0]" = "11"
+	register "PcieClkSrcClkReq[0]" = "0"
+
    # PCIe port 13 for M.2 2280 SSD
    register "PcieRpEnable[12]" = "1"
    register "PcieRpLtrEnable[12]" = "1"
-	register "PcieClkSrcUsage[4]" = "12"
-	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcUsage[2]" = "12"
+	register "PcieClkSrcClkReq[2]" = "2"

# GPIO PM programming
    register "gpio_override_pm" = "1"
@@ -359,7 +364,7 @@
    		end
    	end # I2C #4
    	device pci 19.1 off end # I2C #5
-		device pci 19.2 off end # UART #2
+		device pci 19.2 on  end # UART #2
    	device pci 1a.0 off end # eMMC
    	device pci 1c.0 off end # PCI Express Port 1 (USB)
    	device pci 1c.1 off end # PCI Express Port 2 (USB)
@@ -373,12 +378,12 @@
    		smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
    	end # PCI Express Port 9
    	device pci 1d.1 on  end # PCI Express Port 10
-		device pci 1d.2 on  end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 on  end # PCI Express Port 12
    	device pci 1d.4 on
    		smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
    	end # PCI Express Port 13 (x4)
-		device pci 1e.0 on  end # UART #0
+		device pci 1e.0 off end # UART #0
    	device pci 1e.1 off end # UART #1
    	device pci 1e.2 off end # GSPI #0
    	device pci 1e.3 off end # GSPI #1