Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42897 )
Change subject: mb/google/volteer: Enable HotPlug on PCIe root port for the SD express ......................................................................
mb/google/volteer: Enable HotPlug on PCIe root port for the SD express
Enable HotPlug for the PCIe root port that the SD express is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime.
BUG=b:156879564 BRANCH=master TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in linux that it is identified as a HotPlug capable root port
Signed-off-by: Nick Chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Nick Chen: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 300fb7e..88aff01 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -86,6 +86,7 @@ # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + register "PcieRpHotPlug[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3"