[coreboot-gerrit] Patch merged into coreboot/master: 989e12b arm: Fix stored PC value when handling exceptions

the following patch was just integrated into master:
commit 989e12bb6387bd06037805dcefa249d998b55b74
Author: Julius Werner 
Date:   Wed May 14 14:53:18 2014 -0700

arm: Fix stored PC value when handling exceptions

ARM processors save the PC value in the Link Register when they handle
    and exception, but they store it with an added offset (depending on the
    exception type). In order to make crashes easier to read and correctly
    support more complicated handlers in libpayload, this patch adjusts the
    saved PC value on exception entry to correct for that offset.

(Note: The value that we now store is what ARM calls the "preferred
    return address". For most exceptions this is the faulting instruction,
    but for software interrupts (SWI) it is the instruction after that. This
    is the way most programs like GDB expect the stored PC address to work,
    so let's leave it at that.)

Numbers taken from the Architecture Reference Manual at the end of
    section B1.8.3.

BRANCH=none
    BUG=chrome-os-partner:18390
    TEST=Provoked a data abort and an undefined instruction in both coreboot
    and depthcharge, confirmed that the PC address was spot on.

Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba
    Original-Signed-off-by: Julius Werner 
    Original-Reviewed-on: https://chromium-review.googlesource.com/199844
    Original-Reviewed-by: Stefan Reinauer 
    Original-Reviewed-by: Vincent Palatin 
    (cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac)
    Signed-off-by: Marc Jones

Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6
    Reviewed-on: http://review.coreboot.org/7992
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks

See http://review.coreboot.org/7992 for details.

-gerrit