Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34423 )
Change subject: soc/amd/picasso: Begin adding FSP support ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34423/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34423/2//COMMIT_MSG@11 PS2, Line 11: e.g. in EDK II,
I do not understand this part. […]
All this entire paragraph is doing is establishing a premise. That is, it's impractical (at the very best) to attempt to port AGESA v9 source for use in coreboot. To do so would require something unacceptable, like somehow combining coreboot and EDK II, or modifying AGESA so dramatically that it wouldn't be supportable from a single codebase.
To answer your question, like Intel FSP, the supplier's reference code is prebuilt within a UDK, into a firmware volume. The External Architecture Spec is on Intel's site, however under the hood the reference code still relies on UEFI type stuff. It's built as libraries and drivers, has a PEI dispatcher to load/run modules, etc.
You've seen the AGESA source in vendorcode; that's v5 and AMD refers to v9 as a complete rewrite for UEFI. The FSP route was chosen because it's an established interface for using code written for a UEFI environment.
https://review.coreboot.org/c/coreboot/+/34423/2//COMMIT_MSG@12 PS2, Line 12: legacy BIOS
What do you mean by “legacy BIOS”?
Anything non-UEFI. That's how v5 was designed. Its interface was intended to minimize disruption for adding into firmware, "call these handful of functions at specifics times"...
I'm glad to reword this to something more descriptive if you'd like.