Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57443 )
Change subject: mb/*/brya/variants/brask: Enable dynamic GPIO PM ......................................................................
mb/*/brya/variants/brask: Enable dynamic GPIO PM
GPIO PM was disabled for brask to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM.
TEST=Boot brask to OS, ensure no TPM errors.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb 1 file changed, 0 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 646309e..76d437c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -20,17 +20,6 @@ # Enable heci communication register "HeciEnabled" = "1"
- # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Enable CNVi BT register "CnviBtCore" = "true"