[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Configure DCACHE_BSP_STACK_SIZE

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36884 )

Change subject: nb/intel/sandybridge: Configure DCACHE_BSP_STACK_SIZE
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nb/intel/sandybridge: Configure DCACHE_BSP_STACK_SIZE

The romstage default is to set stack guards at 0x2000 below end
of stack. The code is now overwrites some of the stack guards
so increase the stack size to a comfortable 0x2800.

Change-Id: I91f559383a987241b343e743d11291f2c100f7f5
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/sandybridge/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/36884/1

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 64ce4d8..288dd09 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -76,6 +76,9 @@
    hex
    default 0xfefe0000

+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2800

if USE_NATIVE_RAMINIT