[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Support to initialize Memory

[Varun Joshi (Code Review)]

Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )

Change subject: soc/intel/tigerlake: Support to initialize Memory
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Patch Set 7:

(4 comments)

https://review.coreboot.org/c/coreboot/+/39847/1/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39847/1/src/soc/intel/tigerlake/inc... 
PS1, Line 63: 	 * ohms of the rcomp resistor attached to the DDR_COMP pins on the DRAM.
> More words fit on the line above.

Done

https://review.coreboot.org/c/coreboot/+/39847/1/src/soc/intel/tigerlake/inc... 
PS1, Line 65: uint16_t rcomp_resistor;
> It was confirmed earlier that rcomp_resistor does not need to be changed from default. […]

Done

https://review.coreboot.org/c/coreboot/+/39847/1/src/soc/intel/tigerlake/inc... 
PS1, Line 71: dq_pins_interleaved
> Yes, I think its required. […]

Done

https://review.coreboot.org/c/coreboot/+/39847/1/src/soc/intel/tigerlake/inc... 
PS1, Line 87: void tigerlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
            : 			   const struct  mb_lpddr4x_cfg *tgl_cfg);
> Thanks Selma!

Done