[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/common/block/spi: Enforce default ROM mapping

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87176?usp=email )

Change subject: soc/amd/common/block/spi: Enforce default ROM mapping
......................................................................

soc/amd/common/block/spi: Enforce default ROM mapping

Make sure that the ROM2 MMIO area starts at flash address 0.

Document 56780

Change-Id: I1fc06517ea496441147375579800f7349e39facc
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/soc/amd/common/block/spi/mmap_boot.c
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/soc/amd/common/block/spi/mmap_boot.c b/src/soc/amd/common/block/spi/mmap_boot.c
index d29af41..6a91719 100644
--- a/src/soc/amd/common/block/spi/mmap_boot.c
+++ b/src/soc/amd/common/block/spi/mmap_boot.c
@@ -3,6 +3,7 @@
 #include <boot_device.h>
 #include <endian.h>
 #include <spi_flash.h>
+#include <amdblocks/spi.h>

#if CONFIG_ROM_SIZE >= (16 * MiB)
 #define ROM_SIZE (16 * MiB)
@@ -18,6 +19,13 @@

const struct region_device *boot_device_ro(void)
 {
+	/*
+	 * The following code assumes that ROM2 is mapped at flash offset 0. This is the default
+	 * configuration currently enforced by soft-straps.
+	 */
+	if (fch_spi_rom_remapping() != 0)
+		die("Non default SPI ROM remapping is not supported!");
+
    return &boot_dev.rdev;
 }