Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 12:
(22 comments)
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG@11 PS6, Line 11: update soc_intel_tigerlake_config struct
Yes, we are planning on adding configs per feature enabling instead of bulk landing. […]
We'll keep the change in structure and add require TGL change to avoid autobuild issue(JSL)
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... PS11, Line 200: /* Statically clock gate 8254 PIT. */ : uint8_t clock_gate_8254; Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/11/src/soc/intel/tigerlake/ch... PS11, Line 204: /* : * PRMRR size setting with below options : * 0x00100000 - 1MiB : * 0x02000000 - 32MiB and beyond : */ Update comments
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 39: GPP_[A:G]
Ack
That's correct according to latest GPIO change
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize
Is this used?
Used by TGL FSP
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 71: SmramMask
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 72: MrcFastBoot
Is this used?
Not used: remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize
Is this used?
Used by TGL FSP
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 74: MmioSize
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 78: DdrFreqLimit
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 82: FreqSaGvLow
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 86: FreqSaGvMid
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 92: SaGv_Disabled, : SaGv_FixedLow, : SaGv_FixedMid, : SaGv_FixedHigh, : SaGv_Enabled,
Are these correct for TGL?
Update according to TGL FSP
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 105: SsicPortEnable
Is this used?
Not used : remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS
Is this really correct?
TGL FSP does not use all but use this Max value to support JSL or other platform.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS
Is this really correct?
TGL FSP does not use all but use this Max value to support JSL or other platform.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 143: GpioIrqRoute
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 145: SciIrqSelect
Is this used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 147: uint8_t TcoIrqSelect; : uint8_t TcoIrqEnable; :
Are these used?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 157: /* Enable VR specific mailbox command : * 00b - no VR specific cmd sent : * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent : * 10b - VR specific cmd sent for PS4 exit issue : * 11b - Reserved */ : uint8_t SendVrMbxCmd;
Is this applicable for TGL?
Not used: Remove
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 180: ProbeTypeDisable = 0x00,
What version of FSP headers?
Match with FSP header
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 221: PLATFORM_POR, : FORCE_ENABLE, : FORCE_DISABLE
Is this correct?
Update based on FSP header