[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Move SATA clock gating to sata.c

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47037 )

Change subject: sb/intel/lynxpoint: Move SATA clock gating to sata.c
......................................................................

sb/intel/lynxpoint: Move SATA clock gating to sata.c

This is where Broadwell does it. It is now done for Lynxpoint-H as well.
Relocate the write for the initial value to where Broadwell does it.

Change-Id: I1c1daf6af08b2de4cbdc48df8fbef68e4d5a9482
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/sata.c
2 files changed, 13 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47037/1

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 10e498a..a168de0 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -282,9 +282,6 @@
 /* LynxPoint LP PCH Power Management init */
 static void lpt_lp_pm_init(struct device *dev)
 {
-	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
-	u32 data;
-
    printk(BIOS_DEBUG, "LynxPoint LP PM init\n");

pci_write_config8(dev, 0xa9, 0x46);
@@ -342,6 +339,7 @@
    RCBA32(0x2b24) = 0x40000005;
    RCBA32(0x2b20) = 0x0005db01;
    RCBA32(0x3a80) = 0x05145005;
+	RCBA32(0x3a84) = 0x00001005;

pci_or_config32(dev, 0xac, 1 << 21);

@@ -350,16 +348,6 @@
    pch_iobp_update(0xED000120, ~0, 0x00240000);
    pch_iobp_update(0xCA000000, ~0, 0x00000009);

-	/* Set RCBA CIR28 0x3A84 based on SATA port enables */
-	data = 0x00001005;
-	/* Port 3 and 2 disabled */
-	if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
-		data |= (1 << 24) | (1 << 26);
-	/* Port 1 and 0 disabled */
-	if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
-		data |= (1 << 20) | (1 << 18);
-	RCBA32(0x3a84) = data;
-
    /* Set RCBA 0x2b1c[29]=1 if DSP disabled */
    if (RCBA32(FD) & PCH_DISABLE_ADSPD)
    	RCBA32_OR(0x2b1c, (1 << 29));
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 460e31d..2eb7dd8 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -156,6 +156,18 @@
    if (pch_is_lp())
    	sata_configure_devslp(config, abar);

+	/*
+	 * Static Power Gating for unused ports
+	 */
+	reg32 = RCBA32(0x3a84);
+	/* Port 3 and 2 disabled */
+	if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
+		reg32 |= (1 << 24) | (1 << 26);
+	/* Port 1 and 0 disabled */
+	if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
+		reg32 |= (1 << 20) | (1 << 18);
+	RCBA32(0x3a84) = reg32;
+
    /* Set Gen3 Transmitter settings if needed */
    if (config->sata_port0_gen3_tx)
    	pch_iobp_update(SATA_IOBP_SP0G3IR, 0,