[coreboot-gerrit] Change in coreboot[master]: cpu/amd/family_10h-family_15h/cache_as_ram.S: Remove obsolete code

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62086 )

Change subject: cpu/amd/family_10h-family_15h/cache_as_ram.S: Remove obsolete code
......................................................................

cpu/amd/family_10h-family_15h/cache_as_ram.S: Remove obsolete code

SSE is already enabled by entry32.S file. BIST and timestamp are
already saved in MMX register. No need to move the values or enable
the SSE again.

Signed-off-by: Michał Żygowski 
Change-Id: I1b908e8fbe0dee50e535c193b2eddf66e16b6c88
---
M src/cpu/amd/family_10h-family_15h/cache_as_ram.S
1 file changed, 0 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/62086/1

diff --git a/src/cpu/amd/family_10h-family_15h/cache_as_ram.S b/src/cpu/amd/family_10h-family_15h/cache_as_ram.S
index 0b353df..076f2d8 100644
--- a/src/cpu/amd/family_10h-family_15h/cache_as_ram.S
+++ b/src/cpu/amd/family_10h-family_15h/cache_as_ram.S
@@ -44,22 +44,8 @@
  */
 .global bootblock_pre_c_entry
 bootblock_pre_c_entry:
-	/* Save the BIST result. */
-	movl	%eax, %ebp
-
-	/*
-	 * For normal part %ebx already contain cpu_init_detected
-	 * from fallback call.
-	 */
-
-cache_as_ram_setup:
    post_code(0xa0)

-	/* Enable SSE. */
-	movl	%cr4, %eax
-	orl	$(3 << 9), %eax
-	movl	%eax, %cr4
-
    /* Figure out the CPU family. */
    cvtsi2sd %ebx, %xmm4
    movl	$0x01, %eax