Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52730 )
Change subject: soc/alderlake: Fix DDR5 boot hang due to incorrect array size ......................................................................
soc/alderlake: Fix DDR5 boot hang due to incorrect array size
The size of spd address and data array should be equal to the no of MRC channels.
BUG=b:180458099 TEST=Boot DDR5 to kernel
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/smbuslib.c 2 files changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/52730/1
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 973eb49..0b50691 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -5,6 +5,7 @@
#include <stdint.h> #include <commonlib/region.h> +#include <soc/meminit.h>
#define SPD_PAGE_LEN 256 #define SPD_PAGE_LEN_DDR4 512 @@ -36,8 +37,8 @@ #define DDR4_SPD_SN_OFF 325
struct spd_block { - u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ - u8 *spd_array[CONFIG_DIMM_MAX]; + u8 addr_map[MRC_CHANNELS]; /* 7 bit I2C addresses */ + u8 *spd_array[MRC_CHANNELS]; /* Length of each dimm */ u16 len; }; diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 17b6377..6fd92f3 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -5,6 +5,7 @@ #include <device/smbus_def.h> #include <device/smbus_host.h> #include "smbuslib.h" +#include <soc/meminit.h>
static void update_spd_len(struct spd_block *blk) { @@ -72,7 +73,7 @@ void get_spd_smbus(struct spd_block *blk) { u8 i; - for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { + for (i = 0 ; i < MRC_CHANNELS ; i++) { if (blk->addr_map[i] == 0) { blk->spd_array[i] = NULL; continue;