[coreboot-gerrit] [M] Change in coreboot[main]: mb/google/brya/var/xol: Configure power limits by battery status

[SH Kim (Code Review)]

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81614?usp=email )

Change subject: mb/google/brya/var/xol: Configure power limits by battery status
......................................................................

mb/google/brya/var/xol: Configure power limits by battery status

When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities. This will check the current battery status and configure
cpu power limits using current PD power value.

BUG=b:328729536
TEST=built and veified MSR PL2/PL4 values using PTAT.

Original power limit configuration for Xol:
MSR PL2: 55W, MSR PL4: 114W.

[When connected 60W adaptor without battery]
Before:
MSR PL2: 55W, MSR PL4: 114W
After:
MSR PL2: 55W, MSR PL4: 60W

[When connected 45W adaptor without battery]
Before:
MSR PL2: 55W, MSR PL4: 114W
After:
MSR PL2: 45W, MSR PL4: 45W

Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d
Signed-off-by: Seunghwan Kim 
---
M src/mainboard/google/brya/variants/xol/Makefile.mk
A src/mainboard/google/brya/variants/xol/ramstage.c
2 files changed, 80 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/81614/1

diff --git a/src/mainboard/google/brya/variants/xol/Makefile.mk b/src/mainboard/google/brya/variants/xol/Makefile.mk
index 641e814..c346b0a 100644
--- a/src/mainboard/google/brya/variants/xol/Makefile.mk
+++ b/src/mainboard/google/brya/variants/xol/Makefile.mk
@@ -3,3 +3,4 @@
 bootblock-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/xol/ramstage.c b/src/mainboard/google/brya/variants/xol/ramstage.c
new file mode 100644
index 0000000..5ccdd63
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/ramstage.c
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+static bool get_pd_power_watts(u32 *watts)
+{
+	int rv;
+	enum usb_chg_type type;
+	u16 volts_mv, current_ma;
+
+	rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
+	if (rv == 0 && type == USB_CHG_TYPE_PD) {
+		/* Detected USB-PD. Base on max value of adapter */
+		*watts = ((u32)current_ma * volts_mv) / 1000000;
+		return true;
+	}
+	
+	return false;
+}
+
+static struct soc_power_limits_config* get_soc_power_limit_config(void)
+{
+	config_t *config = config_of_soc();
+	size_t i;
+	struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT);
+	uint16_t sa_pci_id;
+	u8 tdp;
+
+	if (sa == NULL)
+		return NULL;
+
+	sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID);
+	if (sa_pci_id == 0xffff)
+		return NULL;
+	
+	tdp = get_cpu_tdp();
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
+				tdp == cpuid_to_adl[i].cpu_tdp) {
+			return &config->power_limits_config[cpuid_to_adl[i].limits];
+		}
+	}
+
+	return NULL;
+}
+
+void variant_devtree_update(void)
+{
+	struct soc_power_limits_config *soc_config = get_soc_power_limit_config();
+	u32 watts;
+
+	if (soc_config == NULL)
+		return;
+	/*
+	 * If battery is not present or battery level is at or below critical threshold
+	 * to boot a platform with the performance efficient configuration, limit PL2
+	 * and PL4 settings. 
+	 */
+	if (!google_chromeec_is_battery_present_and_above_critical_threshold()) {
+		if (get_pd_power_watts(&watts)) {
+			printk(BIOS_INFO, "override PL2 and PL4 settings to %d watts\n",
+					watts);
+
+			if (soc_config->tdp_pl2_override > watts)
+				soc_config->tdp_pl2_override = watts;
+
+			if (soc_config->tdp_pl4 > watts)
+				soc_config->tdp_pl4 = watts;
+		}
+	}
+}