[coreboot-gerrit] Change in coreboot[master]: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40523 )

Change subject: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40523/5/src/soc/intel/xeon_sp/skx/c... 
File src/soc/intel/xeon_sp/skx/cpu.c:

https://review.coreboot.org/c/coreboot/+/40523/5/src/soc/intel/xeon_sp/skx/c... 
PS5, Line 75: 	/* If socket_index is 0 then all PPIN have been saved. */
I wonder if this logic is over complicated. We want to read PPIN MSR from one core/thread of each socket. So we can just read PPIN MSR of core 0, thread 0 of each socket (or PBSP, SBSP).