Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 12:
(18 comments)
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 39: GPP_[A:G]
That's correct according to latest GPIO change
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 70: PlatformMemorySize
Used by TGL FSP
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 71: SmramMask
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 72: MrcFastBoot
Not used: remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 73: TsegSize
Used by TGL FSP
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 74: MmioSize
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 78: DdrFreqLimit
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 82: FreqSaGvLow
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 86: FreqSaGvMid
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 92: SaGv_Disabled, : SaGv_FixedLow, : SaGv_FixedMid, : SaGv_FixedHigh, : SaGv_Enabled,
Update according to TGL FSP
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 105: SsicPortEnable
Not used : remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 123: CONFIG_MAX_ROOT_PORTS
TGL FSP does not use all but use this Max value to support JSL or other platform.
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 126: CONFIG_MAX_ROOT_PORTS
TGL FSP does not use all but use this Max value to support JSL or other platform.
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 143: GpioIrqRoute
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 145: SciIrqSelect
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 147: uint8_t TcoIrqSelect; : uint8_t TcoIrqEnable; :
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 157: /* Enable VR specific mailbox command : * 00b - no VR specific cmd sent : * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent : * 10b - VR specific cmd sent for PS4 exit issue : * 11b - Reserved */ : uint8_t SendVrMbxCmd;
Not used: Remove
Done
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 167: /* Statically clock gate 8254 PIT. */ : uint8_t clock_gate_8254; Note used: Remove