the following patch was just integrated into master: commit 31682364ba062fb3cbf4ff3b0ad7cbdb7b5daae1 Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sat Jan 30 23:34:51 2016 -0600
nb/amd/mct_ddr3: Work around RDIMM training failure
Under certain conditions, not elucidated in the BKDG, an extra memclock of CAS write latency is required.
The only reliable way I have found to detect when this is required is to try training without the delay, and if DQS position training fails, adding the delay and retraining.
This is probably related in some form or another to the badly broken DQS Write Early algorithm given in the BKDG.
Change-Id: Idfaca1b3da3f45793d210980e952ccdfc9ba1410 Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com Reviewed-on: https://review.coreboot.org/13531 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand noreply@raptorengineeringinc.com Reviewed-by: Martin Roth martinroth@google.com
See https://review.coreboot.org/13531 for details.
-gerrit