Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38601 )
Change subject: asus/p2b*: Declare _SB.PCI0.MBRS in DSDT ......................................................................
asus/p2b*: Declare _SB.PCI0.MBRS in DSDT
sb/intel/i82371eb/isa.c has code that fills this path with CPU info. Because it was not declared in the DSDT, Linux kernel 4.4.18 as used in Slackware 14.2 complains.
Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38601 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asus/p2b/dsdt.asl 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 05af720..5bc5d72 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -166,6 +166,7 @@
}) #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> + #include <southbridge/intel/i82371eb/acpi/isabridge.asl>
/* Begin southbridge block */ Device (PX40) @@ -184,6 +185,7 @@ Device (SYSR) { Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate ()