Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )
Change subject: soc/intel/tigerlake: Support to initialize Memory ......................................................................
Patch Set 15:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... PS12, Line 308: unsigned
const
Done
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... PS12, Line 309: unsigned
const
Done
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... PS12, Line 320: struct spd_block blk = { : .addr_map[0] = spd->smbus_info[0].addr_dimm0, : .addr_map[1] = spd->smbus_info[0].addr_dimm1, : .addr_map[2] = spd->smbus_info[1].addr_dimm0, : .addr_map[3] = spd->smbus_info[1].addr_dimm1, : }; : : read_smbus_spd(&blk, &spd_len, &spd_data0, &spd_data1);
This function should be able to handle all three memory topologies. I am thinking something like: […]
Done
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... PS12, Line 337: */
Please format the comment correctly by aligning the asterisks and adding a dot after an asterisk. […]
Done
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... PS12, Line 339: for (unsigned int i = 0; i < DDR4_CHANNELS; i++) { : for (int b = 0; b < DQ_SODIMM_SLOT; b++) { : init_dq_upds(mem_cfg, 4i+b, &board_cfg->dq_map[i][DQ_PER_CHANNEL*b]); : init_dqs_upds(mem_cfg, 4i+b, &board_cfg->dqs_map[i][DQS_PER_CHANNEL*b]); : } : }
This will have to be updated as per latest changes.
Done