Thaminda Edirisooriya (thaminda@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11368
-gerrit
commit 914be6a4e1a0092808fc42c9bed0c482fec6abcb Author: Thaminda Edirisooriya thaminda@google.com Date: Wed Aug 26 14:54:31 2015 -0700
riscv-trap-handling: Add implementation for trap calls in riscv
RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c
Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya thaminda@google.com --- src/arch/riscv/include/arch/errno.h | 66 ++++++++ src/arch/riscv/include/arch/exception.h | 22 +++ src/arch/riscv/include/spike_util.h | 13 +- src/arch/riscv/trap_handler.c | 195 +++++++++++++++++++++++ src/arch/riscv/trap_util.S | 22 ++- src/mainboard/emulation/spike-riscv/spike_util.c | 139 ++++++++++++++++ 6 files changed, 450 insertions(+), 7 deletions(-)
diff --git a/src/arch/riscv/include/arch/errno.h b/src/arch/riscv/include/arch/errno.h new file mode 100644 index 0000000..6f80ee5 --- /dev/null +++ b/src/arch/riscv/include/arch/errno.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _RISCV_ERRNO_BASE_H +#define _RISCV_ERRNO_BASE_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#endif diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index befab1f..8ed295d 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -32,8 +32,30 @@
#include <stdint.h>
+typedef struct +{ + long gpr[32]; + long status; + long epc; + long badvaddr; + long cause; + long insn; +} trapframe; + +typedef uint32_t insn_t; + +typedef struct { + uintptr_t error; + insn_t insn; +} insn_fetch_t; + static inline void exception_init(void) { }
+void trap_handler(trapframe* tf); +void handleSupervisorCall(trapframe* tf); +//void handleMisalignedLoad(trapframe *tf); +void handleMisalignedStore(trapframe *tf); + #endif diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/spike_util.h index a9d14cc..2d6355b 100644 --- a/src/arch/riscv/include/spike_util.h +++ b/src/arch/riscv/include/spike_util.h @@ -1,15 +1,16 @@ /* - * This file is part of the coreboot project. + * Early initialization code for riscv * - * Copyright (C) 2013 The ChromiumOS Authors + * Copyright 2015 Google Inc. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c new file mode 100644 index 0000000..ce19d7a --- /dev/null +++ b/src/arch/riscv/trap_handler.c @@ -0,0 +1,195 @@ +/* + * Early initialization code for riscv + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <arch/exception.h> +#include <spike_util.h> +#include <string.h> + +#define HART_ID 0 +#define CONSOLE_PUT 1 +#define SEND_DEVICE_REQUEST 2 +#define RECEIVE_DEVICE_RESPONSE 3 +#define SEND_IPI 4 +#define CLEAR_IPI 5 +#define SHUTDOWN 6 +#define SET_TIMER 7 +#define QUERY_MEMORY 8 + +int loopBreak2 = 1; + +void handleSupervisorCall(trapframe *tf) { + uintptr_t call = tf->gpr[17]; + uintptr_t arg0 = tf->gpr[10]; + uintptr_t arg1 = tf->gpr[11]; + uintptr_t returnValue; + switch(call) { + case HART_ID: + printk(BIOS_DEBUG, "Getting hart id...\n"); + returnValue = mcall_hart_id(); + break; + case CONSOLE_PUT: + returnValue = mcall_console_putchar(arg0); + break; + case SEND_DEVICE_REQUEST: + printk(BIOS_DEBUG, "Sending device request...\n"); + returnValue = mcall_dev_req((sbi_device_message*) arg0); + break; + case RECEIVE_DEVICE_RESPONSE: + printk(BIOS_DEBUG, "Getting device response...\n"); + returnValue = mcall_dev_resp(); + break; + case SEND_IPI: + printk(BIOS_DEBUG, "Sending IPI...\n"); + returnValue = mcall_send_ipi(arg0); + break; + case CLEAR_IPI: + printk(BIOS_DEBUG, "Clearing IPI...\n"); + returnValue = mcall_clear_ipi(); + break; + case SHUTDOWN: + printk(BIOS_DEBUG, "Shutting down...\n"); + returnValue = mcall_shutdown(); + break; + case SET_TIMER: + printk(BIOS_DEBUG, "Setting timer...\n"); + returnValue = mcall_set_timer(arg0); + break; + case QUERY_MEMORY: + printk(BIOS_DEBUG, "Querying memory, CPU #%lld...\n", arg0); + returnValue = mcall_query_memory(arg0, (memory_block_info*) arg1); + break; + default: + printk(BIOS_DEBUG, "ERROR! Unrecognized system call\n"); + returnValue = 0; + break; // note: system call we do not know how to handle + } + tf->gpr[10] = returnValue; + write_csr(mepc, read_csr(mepc) + 4); + asm volatile("j supervisor_call_return"); +} + +void trap_handler(trapframe *tf) { + write_csr(mscratch, tf); + int cause = 0; + void* epc = 0; + void* badAddr = 0; + + // extract cause + asm("csrr t0, mcause"); + asm("move %0, t0" : "=r"(cause)); + + // extract faulting Instruction pc + epc = (void*) tf->epc; + + // extract bad address + asm("csrr t0, mbadaddr"); + asm("move %0, t0" : "=r"(badAddr)); + + switch(cause) { + case 0: + printk(BIOS_DEBUG, "Trap: Instruction address misaligned\n"); + break; + case 1: + printk(BIOS_DEBUG, "Trap: Instruction access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Address: %p\n", badAddr); + break; + case 2: + printk(BIOS_DEBUG, "Trap: Illegal instruction\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Address: %p\n", badAddr); + break; + case 3: + printk(BIOS_DEBUG, "Trap: Breakpoint\n"); + break; + case 4: + printk(BIOS_DEBUG, "Trap: Load address misaligned\n"); + //handleMisalignedLoad(tf); + break; + case 5: + printk(BIOS_DEBUG, "Trap: Load access fault\n"); + break; + case 6: + printk(BIOS_DEBUG, "Trap: Store address misaligned\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); + handleMisalignedStore(tf); + break; + case 7: + printk(BIOS_DEBUG, "Trap: Store access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); + break; + case 8: + printk(BIOS_DEBUG, "Trap: Environment call from U-mode\n"); + break; + case 9: + // Don't print so we make console putchar calls look the way they should + // printk(BIOS_DEBUG, "Trap: Environment call from S-mode\n"); + handleSupervisorCall(tf); + break; + case 10: + printk(BIOS_DEBUG, "Trap: Environment call from H-mode\n"); + break; + case 11: + printk(BIOS_DEBUG, "Trap: Environment call from M-mode\n"); + break; + default: + printk(BIOS_DEBUG, "Trap: Unknown cause\n"); + break; + } + printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + printk(BIOS_DEBUG, "looping...\n"); + while(1); +} + +void handleMisalignedStore(trapframe *tf) { + printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + insn_t faultingInstruction = 0; + uintptr_t faultingInstructionAddr = tf->epc; + uintptr_t misalignedMask = 0x4; + uintptr_t misalignedInstruction = faultingInstructionAddr & misalignedMask; + asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr)); + asm("lw t0, 0(t0)"); + asm("move %0, t0" : "=r"(faultingInstruction)); + printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); + insn_t widthMask = 0x7000; + insn_t memWidth = (faultingInstruction & widthMask) >> 12; + insn_t srcMask = 0x1F00000; + insn_t srcRegister = (faultingInstruction & srcMask) >> 20; + printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth); + if (memWidth == 3) { + // store double, handle the issue + void* badAddress = (void*) tf->badvaddr; + long valueToStore = tf->gpr[srcRegister]; + memcpy(badAddress, &valueToStore, 8); + } else { + // panic, this should not have happened + printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n"); + while(1); + } + + // return to where we came from + write_csr(mepc, read_csr(mepc) + 4); + asm volatile("j machine_call_return"); +} diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 912bea8..9701aaf 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -1,3 +1,23 @@ +/* + * Early initialization code for riscv + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + #include <bits.h> .macro restore_regs # restore x registers @@ -101,7 +121,7 @@ supervisor_trap_entry: trap_entry: csrw mscratch, sp 1:addi sp,sp,-320 - save_tf_ + save_tf move a0,sp jal trap_handler .global supervisor_call_return diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index b34ff4a..1ee8b77 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -1,4 +1,143 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + #include <spike_util.h> +#include <arch/errno.h> +#include <atomic.h> +#include <string.h> +#include <console/console.h> + +uintptr_t translate_address(uintptr_t vAddr) { + // TODO: implement the page table translation algorithm + //uintptr_t pageTableRoot = read_csr(sptbr); + uintptr_t physAddrMask = 0xfffffff; + uintptr_t translationResult = vAddr & physAddrMask; + printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n", vAddr, translationResult); + return translationResult; +} + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) +{ + uintptr_t physicalAddr = translate_address((uintptr_t) p); + memory_block_info *info = (memory_block_info*) physicalAddr; + if (id == 0) { + info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later + info->size = 0x7F000000 - info->base; + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + //if (recipient >= num_harts) + //return -1; + + if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { + mb(); + write_csr(send_ipi, recipient); + } + + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + while (1) write_csr(mtohost, 1); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + write_csr(mtimecmp, when); + #ifndef __riscv64 + write_csr(mtimecmph, when >> 32); + #endif + clear_csr(mip, MIP_STIP); + set_csr(mie, MIP_MTIP); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; + + while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); + + m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; + HLS()->device_request_queue_head = m; + HLS()->device_request_queue_size++; + + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + htif_interrupt(0, 0); + + sbi_device_message* m = HLS()->device_response_queue_head; + if (m) { + //printm("resp %p\n", m); + sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); + HLS()->device_response_queue_head = next; + if (!next) { + HLS()->device_response_queue_tail = 0; + + // only clear SSIP if no other events are pending + clear_csr(mip, MIP_SSIP); + mb(); + if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); + } + } + return (uintptr_t)m; +} + +uintptr_t mcall_hart_id(void) +{ + return HLS()->hart_id; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +}
uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { uintptr_t fromhost = swap_csr(mfromhost, 0);