[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47198 )

Change subject: mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47198/5/src/mainboard/google/voltee... 
File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/47198/5/src/mainboard/google/voltee... 
PS5, Line 418:  so it can participate in power management.
Where does the power management happen? Is it in the OS (part of ACPI)?

Shouldn't this port be disabled and turned off in coreboot/FSP?