Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/21701
Change subject: arch/x86: CAR setup CQOS ......................................................................
arch/x86: CAR setup CQOS
Enable CQOS on Geminilake.
In Appololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF.
Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK.
Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right bits.
BUG=None TEST= Build for Geminilake platform i.e., glkrvp & check for successful CAR setup. Even verified the same on APL platfrom i.e., on Reef
Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 29 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21701/4
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 94e2694..9475c8c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -255,6 +255,25 @@ .global car_cqos car_cqos: /* + * Create CBM_LEN_MASK based on CBM_LEN + * Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0] + */ + mov $0x10, %eax + mov $0x2, %ecx + cpuid + and $0xF, %eax + add $1, %al + + mov $1, %ebx + xor %ecx, %ecx + mov %al, %cl + shl %cl, %ebx + sub $1, %ebx + + /* Store the CBM_LEN_MASK in mm3 for later use. */ + movd %ebx, %mm3 + + /* * Disable both L1 and L2 prefetcher. For yet-to-understood reason, * prefetchers slow down filling cache with rep stos in CQOS mode. */ @@ -284,7 +303,7 @@ /* Set this mask for initial cache fill */ mov $MSR_L2_QOS_MASK(0), %ecx rdmsr - mov %bl, %al + mov %ebx, %eax wrmsr
/* Set CLOS selector to 0 */ @@ -297,8 +316,15 @@ mov $MSR_L2_QOS_MASK(1), %ecx rdmsr /* Invert bits that are to be used for cache */ - mov %bl, %al - xor $~0, %al /* invert 8 bits */ + mov %ebx, %eax + xor $~0, %eax /* invert 32 bits */ + + /* + * Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit + * Mask Length. + */ + movd %mm3, %ebx + and %ebx, %eax wrmsr
post_code(0x26)