Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Varun Joshi, Varun Joshi, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39865
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Reorganize memory initialization support ......................................................................
soc/intel/tigerlake: Reorganize memory initialization support
This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. 2. spd_info structure is organized to allow mixed topologies as well. 3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is successful.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 --- M src/mainboard/google/volteer/romstage.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/intel/tglrvp/romstage_fsp_params.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c M src/soc/intel/tigerlake/include/soc/meminit_tgl.h M src/soc/intel/tigerlake/meminit_tgl.c 9 files changed, 433 insertions(+), 221 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39865/6