[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies

[Matt DeVillier (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Eric Lai, Fred Reitberger, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74288

to look at the new patch set (#5).

Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
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soc/amd/common/blk/pcie: Program LTR max latencies

PCIe bridges need to provide the LTR (latency tolerance reporting)
maximum snoop/non-snoop values so that they are inherited by downstream
PCIe devices which support and enable LTR. Without this, downstream
devices cannot have LTR enabled, which is a requirement for supporting
PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior,
including some devices refusing to enter L1 low power modes at all.

Program the max snoop/non-snoop latency values for all PCIe bridges
using the same value used by AGESA/FSP, 1.049ms.

BUG=b:265890321
TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure
LTR is enabled, latency values are correctly set, and that device
power draw at idle is in the expected range (<25 mW).

Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Signed-off-by: Matt DeVillier 
---
M src/soc/amd/common/block/pci/pcie_gpp.c
1 file changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74288/5