27 Jan
2020
27 Jan
'20
4:10 p.m.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36517 )
Change subject: sc7180: Add SPI QUP driver ......................................................................
Patch Set 20: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36517/20/src/soc/qualcomm/sc7180/qu... File src/soc/qualcomm/sc7180/qupv3_spi.c:
https://review.coreboot.org/c/coreboot/+/36517/20/src/soc/qualcomm/sc7180/qu... PS20, Line 180: write32(®s->spi_cpol, 0); I see you took the disable_dfs stuff out here. Can you explain how exactly frequency selection works with DFS enabled? I just want to make sure the assumptions we have made about the clock speed here still hold.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09
Gerrit-Change-Number: 36517
Gerrit-PatchSet: 20
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