Xi Chen has uploaded a new patch set (#48) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44711 )
Change subject: soc/mediatek/mt8192: Add DDR mode register init
......................................................................
soc/mediatek/mt8192: Add DDR mode register init
Signed-off-by: Huayang Duan huayang.duan@mediatek.com
Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/dramc_dvfs.c
M src/soc/mediatek/mt8192/dramc_pi_basic_api.c
3 files changed, 409 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44711/48
--
To view, visit
https://review.coreboot.org/c/coreboot/+/44711
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5
Gerrit-Change-Number: 44711
Gerrit-PatchSet: 48
Gerrit-Owner: CK HU
ck.hu@mediatek.com
Gerrit-Reviewer: Duan huayang
huayang.duan@mediatek.com
Gerrit-Reviewer: Hung-Te Lin
hungte@chromium.org
Gerrit-Reviewer: Martin Roth
martinroth@google.com
Gerrit-Reviewer: Patrick Georgi
pgeorgi@google.com
Gerrit-Reviewer: Xi Chen
xixi.chen@mediatek.com
Gerrit-Reviewer: Yidi Lin
yidi.lin@mediatek.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-CC: Yu-Ping Wu
yupingso@google.com
Gerrit-MessageType: newpatchset