[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Relocate read to TPM base address

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45390 )

Change subject: nb/intel/x4x: Relocate read to TPM base address
......................................................................

nb/intel/x4x: Relocate read to TPM base address

Other northbridges do it at the start of raminit. Also, since the TPM
access register is 8 bits wide, use 8-bit ops instead of 32-bit ops.

This register works the same for all TXT-enabled northbridges: If the
TPM access register is valid, and the establishment bit (bit 0) is set,
then a DRTM has not been established on the platform (or the TPM is not
present), and the memory will be unlocked. If bit 0 is clear, then the
memory may remain locked depending on whether it could contain secrets.

Change-Id: Ic36a2810a861758ce733fe80c4e555439e2ffb7b
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/x4x/bootblock.c
M src/northbridge/intel/x4x/raminit.c
2 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45390/1

diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index baa4ae3..e83a2b8 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

#include <arch/bootblock.h>
-#include <arch/mmio.h>
 #include <device/pci_ops.h>

#include "x4x.h"
@@ -9,9 +8,6 @@

void bootblock_early_northbridge_init(void)
 {
-	/* Disable LaGrande Technology (LT) */
-	read32((void *)TPM_BASE_ADDRESS);
-
    const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
    pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
 }
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index a62771d..6536fbf 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

+#include <arch/mmio.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
 #include <cbmem.h>
@@ -616,6 +617,9 @@
    timestamp_add_now(TS_BEFORE_INITRAM);
    printk(BIOS_DEBUG, "Setting up RAM controller.\n");

+	/* Disable LaGrande Technology (LT) */
+	read8((void *)TPM_BASE_ADDRESS);
+
    pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);

memset(&s, 0, sizeof(struct sysinfo));