[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST

[Krishna P Bhat D (Code Review)]

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32110

Change subject: mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST
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mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST

GPP_A12 is being GPIO padlocked and cannot used in kernel. Unlock the
GPIO pads to export this pin in kernel to be used as FPMCU_RST.
GPP_A_12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay
resuming to S0. If this pad is not locked and platform was not initially
designed for this functionality, malware could reconfigure this pads
setting under OS (switch to Native3), which would make platform not able
to resume until G3 is applied. To prevent misuse of this pad,
re-configure this pad before entering S3 and S5 to guarantee that the
pad configuration is correct.

BUG=b:128686027

Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4
Signed-off-by: Krishna Prasad Bhat 
---
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32110/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index b974e49..8529d5916 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -411,8 +411,12 @@
    return gpio_table;
 }

-/* Default GPIO settings before entering sleep. */
+/*
+ * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL
+ * as GPO before entering sleep.
+ */
 static const struct pad_config default_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 };

/*
@@ -421,6 +425,7 @@
  * turn off EN_PP3300_WWAN.
  */
 static const struct pad_config s5_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
    PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
 };

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 6173403..57d004f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -328,6 +328,9 @@

/* Set TccActivationOffset */
    tconfig->TccActivationOffset = config->tcc_offset;
+
+	/* Unlock all GPIO pads */
+	tconfig->PchUnlockGpioPads = 1;
 }

/* Mainboard GPIO Configuration */