[coreboot-gerrit] Change in coreboot[master]: google/fizz: Set Pmax value based on SKU id

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/23576

Change subject: google/fizz: Set Pmax value based on SKU id
......................................................................

google/fizz: Set Pmax value based on SKU id

BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp

Change-Id: I47aa7f363781ae877e29bcebf9fae4d59b98027f
Signed-off-by: Shelley Chen 
---
M src/mainboard/google/fizz/mainboard.c
M src/soc/intel/skylake/chip_fsp20.c
2 files changed, 10 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/23576/1

diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index e4d2199..0d97fd4 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -41,6 +41,8 @@
 #define FIZZ_PSYSPL2_U42    90
 #define FIZZ_MAX_TIME_WINDOW 6
 #define FIZZ_MIN_DUTYCYCLE   4
+#define FIZZ_PMAX_U42       120
+#define FIZZ_PMAX_U22       91
 /*
  * For type-C chargers, set PL2 to 90% of max power to account for
  * cable loss and FET Rdson loss in the path from the source.
@@ -137,7 +139,8 @@
  */
 static void mainboard_set_power_limits(u32 *pl2_val, u32 *psyspl2_val,
    			       u32 *psyspl3_val, u32 *psyspl3_time_val,
-				       u32 *psyspl3_dutycycle_val, u32 *pl4_val)
+				       u32 *psyspl3_dutycycle_val, u32 *pl4_val,
+				       u16 *pmax_val)
 {
    enum usb_chg_type type;
    u32 watts;
@@ -150,8 +153,11 @@

/* PL2 value is sku-based, no matter what charger we are using */
    pl2 = FIZZ_PL2_U22;
-	if ((1 << sku) & u42_mask)
+	*pmax_val = FIZZ_PMAX_U22;
+	if ((1 << sku) & u42_mask) {
    	pl2 = FIZZ_PL2_U42;
+		*pmax_val = FIZZ_PMAX_U42;
+	}
    *psyspl3_val = *pl4_val = 0;

/* If we can't get charger info or not PD charger, assume barrel jack */
@@ -269,7 +275,7 @@
    mainboard_set_power_limits(&conf->tdp_pl2_override, &conf->tdp_psyspl2,
    			   &conf->tdp_psyspl3, &conf->tdp_psyspl3_time,
    			   &conf->tdp_psyspl3_dutycycle,
-				   &conf->tdp_pl4);
+				   &conf->tdp_pl4, &conf->psys_pmax);

set_bj_adapter_limit();

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index ce1ad4c..3660f43 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -108,6 +108,7 @@
    /* Set PsysPmax if it is available from DT */
    if (config->psys_pmax) {
    	/* PsysPmax is in unit of 1/8 Watt */
+		printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
    	tconfig->PsysPmax = config->psys_pmax * 8;
    }